スライドのつくりかた

わくわく☆さいしんえーあい活用術 「なんかそれっぽい」スライドを生成してみよう！ ～しごとやだはたらきたくないもうまじむりリスカしｙ（ry ～ @ds54e

やりかた 1. ChatGPT Pro に課金する（諭吉×３） 2. Pro に Deep Research させる 3. レポートをPDF出力する 4. PDF → Markdownに変換する 5. Google AI Pro に課金する (三千円） 6. Gemini ProにMarkdown形式のレポート を投げて「スライドにして」と指示する 7. 結果をパワポにひたすらコピペ 8. Imagenで各ページ用の画像も作っても らって、スライドにペタペタする 9. ☆完成☆ Can you make a report to propose a new verification strategy with the top-down approach? Please refer to attached materials if necessary. The report will eventually be submitted to our managers of verification team. So, the contents have to be looked like something innovative to them. Our device contains GPIO, I2C interface to read/write registers, Crystal oscillator and Frac-N PLL, LVCOMS driver.

A Top-Down Verification Strategy for Mixed-Signal IP Enabling Early Verification to Reduce Risk & Accelerate Schedules Target IPs: Fractional-N PLL, Crystal Oscillator, and other Analog/Mixed-Signal (AMS) blocks.

The Problem: "Flying Blind" with the Bottom-Up Approach The traditional method of waiting for final transistor-level schematics creates a major bottleneck and introduces significant risk. • Current Flow: Bottom-Up (Transistor-level SPICE → Late System Integration) • Key Pain Points: • Verification Bottleneck: Verification is blocked, waiting for the analog design to be completed. • Late Bug Discovery: Over 60% of SoC re-spins are caused by mixed-signal integration errors found too late. • Limited Coverage: Manual SPICE simulations are extremely slow and cannot provide automated, metric-driven functional coverage. • The Cost: • Time: 8-10 week schedule slips. • Money: $5-10M per re-spin.

The Solution: A Top-Down, Model-Driven Strategy We propose shifting from verifying at the end to a continuous verification process that starts on Day 1. • The Core Idea: Begin verification early using high-level behavioral models derived directly from the specification. • How It Works: 1. Model: Create behavioral models of analog IP (PLL, Oscillator) in SystemVerilog (RNM) and Verilog-AMS. 2. Integrate: Place these models into a UVM testbench alongside the digital RTL. 3. Verify: Simulate the full-chip behavior in a fast, digital-centric environment (Xcelium), finding integration bugs months earlier. • The Result: Verification runs in parallel with design, not after it.

Core Technologies of the Proposed Strategy This methodology is built on three proven pillars to achieve speed, accuracy, and rigor. • SystemVerilog Real Number Modeling (RNM) • • Purpose: For fast, functional simulation of analog behavior. Represents signals like voltage or frequency as real values within the digital simulator. Benefit: Enables massive performance gains and regression testing. • Verilog-AMS Behavioral Models • • Purpose: For higher-fidelity modeling where physicsbased behavior is critical. Benefit: Accurately captures complex analog dynamics like control loop stability or oscillator startup. • Universal Verification Methodology (UVM) • • Purpose: To automate tests and provide rigorous, metric-driven sign-off. Benefit: Applies powerful digital verification techniques (constrained-random, assertions, coverage) to the mixed-signal domain.

Why Real Number Modeling (RNM) is a Game-Changer RNM allows us to treat analog blocks like digital IP within our existing verification flow. • Blazing Fast Performance: • RNM simulations are 10x - 1000x faster than SPICE. • A case study showed simulation times dropping from 2 days to 20 minutes, enabling 5000+ regression runs per day. • Start Verification Immediately: • Models are created from specs, decoupling the verification schedule from the analog design timeline. • Seamless Digital Tool Integration: • Runs entirely in a standard digital simulator (Xcelium). • Leverages our full UVM ecosystem, including assertions (SVA), coverage analysis, and automated regressions.

Using Verilog-AMS for Targeted Accuracy For critical analog behaviors, we will use VerilogAMS to achieve higher fidelity without sacrificing the overall strategy's speed. • When to Use It: For behavior that is difficult to model in an event-driven RNM context. • Our Planned Use Cases: • PLL Loop Dynamics: Accurately model the phase detector, charge pump, and loop filter to verify lock transients and stability. • Crystal Oscillator Startup: Simulate the physical growth of oscillation from noise to verify startup time and interaction with digital logic. • Hybrid Approach: We will use Verilog-AMS models as a "golden reference" to create and calibrate our faster RNM models for largescale regressions.

Applying UVM for Rigorous Mixed-Signal Verification
By modeling the analog IP, we can finally apply the full
power of UVM to what was once a "black box".
• Constrained-Random Stimulus:
• Randomize PLL frequencies, power cycles, and
I2C register configurations to find unexpected
corner-case bugs.
• Assertion-Based Verification (SVA):
• Write self-checking assertions for analog
properties.
• Example: assert property (@(posedge clk)
pll_enable |-> s_eventually (pll_lock_status
== 1));

• Functional Coverage & Metric-Driven Sign-off:
• Define covergroups to track verification of
analog states (e.g., lock/unlock), frequency
ranges, and VCTRL levels. This gives us a
quantifiable measure of verification
completeness.

Example in Action: Verifying a Fractional-N PLL Let's see how this works in practice. • Scenario 1: Lock Time & Control Voltage (VCTRL) Range • Stimulus: A UVM sequence randomly programs different target frequencies via the I2C agent. • Checks (Assertions / Scoreboard): 1. Verify the lock indicator asserts within the spec time (e.g., < 50µs). 2. Assert that the VCTRL model value never saturates at the power rails. • Scenario 2: Stress Testing • Stimulus: A test performs rapid, random frequency hopping for thousands of cycles and injects jitter on the reference clock. • Checks: Assert that the PLL never loses lock unexpectedly or that its internal state machine becomes unstable.

The Payoff: Reduced Risk & Predictable Schedules Adopting this strategy provides tangible benefits across the project lifecycle. • Early Bug Detection: Find and fix critical integration bugs months earlier, when fixes are cheap. • Faster Verification Cycles: Run comprehensive mixed-signal regressions overnight, not over weeks. • Improved Confidence & Quality: Use quantifiable coverage metrics for a clear, predictable sign-off. • Schedule Predictability: Decouple the verification schedule from the analog design critical path for a higher chance of first-pass silicon success. • Enhanced Team Collaboration: Create a common, executable framework for analog and digital teams to work together.

Conclusion & Next Steps The proposed top-down strategy is a modern, practical solution to the growing challenge of mixed-signal verification. • We Propose: A top-down, model-driven verification methodology. • By Combining: The speed of RNM, the accuracy of Verilog-AMS, and the rigor of UVM. • We Will Achieve: • Earlier bug detection. • Accelerated project schedules. • Increased confidence in our mixed-signal designs. This is an investment in up-front modeling and automation that will pay for itself by mitigating costly backend risks and delays.

今回のまとめ • 何かわりとそれっぽいのが出来上がって草（なんも知らん人ならだませそう） ← 雑な指示を出す怠惰なニンゲンの図 ↓ AIにわかられる情けない人類